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MaxxBot
Oct 6, 2003

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I remember when Zen 1 came out they claimed that AM4 would last through 2020 so I'd assume yeah unless that's changed.

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Malcolm XML
Aug 8, 2009

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Doubt zen3 will have pcie4 then since it's really much harder to deal with that pcie3 unless they future proofed the pcb and sockets.

Also it's pointless for home uses unless you desperately need massive bandwidth to your ssd or gpu

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It's an old xeon but for the models I'm running I'm not hitting any memory bound issues. I'm running FDS and the fire calculations end up very intense. In the past I'm only seen memory become a problem on a very large model at the start of the run but once the fans start in the model the cpus would always sit at 100%. Even NIST who wrote the software suggest only running as many threads as cpu cores because memory latency isn't an issue.
As I understand it, the usual CPU utilisation number shown doesn't tell if the CPU is memory bound. A CPU is 'busy' whether it is performing instructions or waiting for data from memory (because it's not in the CPU caches). Any CPU utilisation drop at the start of the run is usually a disk IO bottleneck when large runs can't be feed in to memory quickly enough.

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Doubt zen3 will have pcie4 then since it's really much harder to deal with that pcie3 unless they future proofed the pcb and sockets.

Also it's pointless for home uses unless you desperately need massive bandwidth to your ssd or gpu

I could see AMD rolling out an "AM4+"/"TR4+" sockets that are just regular AM4/TR4 except the boards have to be validated to run at PCIe 4 speeds. Probably only high-end enthusiast boards would bother on the AM4 side, but I could see TR4 vendors adopting PCIe 4 as a standard feature for the next generation of boards.

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As I understand it, the usual CPU utilisation number shown doesn't tell if the CPU is memory bound. A CPU is 'busy' whether it is performing instructions or waiting for data from memory (because it's not in the CPU caches). Any CPU utilisation drop at the start of the run is usually a disk IO bottleneck when large runs can't be feed in to memory quickly enough.

I'd eliminated disk bottleneck so that wasn't an issue as the model loads entirely into ram.

In terms of cpu utilisation I've seen a talk by a coder for Netflix in relation to that. From testing I've done the halt while waiting for cache misses doesn't seem to be an issue either.

e: AMD have suggested mixed integer and fp workload ipc is increased by29%.

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Oct 23, 2004

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I could see AMD rolling out an "AM4+"/"TR4+" sockets that are just regular AM4/TR4 except the boards have to be validated to run at PCIe 4 speeds. Probably only high-end enthusiast boards would bother on the AM4 side, but I could see TR4 vendors adopting PCIe 4 as a standard feature for the next generation of boards.

PCIe 4 would need a new socket and pinout most likely, as the voodoo they do to get the signal to not poo poo out over 10 inches of busy and noisy motherboard isn't easy or cheap.

They might do something wierd like first slot 4.0 rest are 3.0 to make it easier, but thats borderline RF engineering, and fuckkkkk that noise.

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SwissArmyDruid
Feb 14, 2014



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Keep in mind this means selling some AM4 products until 2020. If, say, the halo products moved to a new socket while 4/6 core chips continued to use AM4, that technically counts as “support”.

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I think again, it'll be an AM4/AM4+ thing, where the APUs trail behind on AM4 until 2020 and the CPUs move to AM4+, socket compatible but superior features and higher cost.

Here is the AM4 socket pinout


There is a not insignificant number of reserved pins, so there still seems to be plenty of feature room for an AM4+ that differentiates itself from AM4. Obviously AM4+ CPUs will be backwards compatible with AM4 but lose out on features if you do so, such as dual PCIEx16 3.0 lanes, Quad Channel, eDRAM, dual 10Gbe or something - basically X570 will actually be worth it to upgrade. Around 2021 I can see everything getting moved to AM5, PCIE5 and DDR5 with the latest generation of APUs on 5nm to wow the gently caress out of everyone with last gen midrange performance for under 250$ or something. Then you'd get EPYC4 on a new socket followed by Ryzen 5000 series (DDR5, PCIE5, Gen5, one more 5 and AMD needs to source presentation music from Daft Punk) and TR 5000 series by late 2021.

No I'm not going to toxx, just seems like a logical extension of AMD's strategy so far. Basically constantly confound Intel by forcing them to introduce features that've been at a premium tier for a lower cost and erode whatever high end advantages Intel purports to have.

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May 15, 2003

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I read somewhere that some version of AM4 will support ddr5 with Zen3, or that there may be two versions of Zen3 for ddr4 and ddr5 seeing as they can move IO off the core die. The latter seems unlikely. What I'm trying to say is that AM4 or a revision thereof is going to be with us for a long time.

I for, one, miss the pentium 3 Sega cartridge.

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Nov 2, 2001
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PCIe 4 would need a new socket and pinout most likely, as the voodoo they do to get the signal to not poo poo out over 10 inches of busy and noisy motherboard isn't easy or cheap.

They might do something wierd like first slot 4.0 rest are 3.0 to make it easier, but thats borderline RF engineering, and fuckkkkk that noise.

They won't need a new socket/pinout for PCIe 4 (or 5); the layout is exactly the same as 3 (and 2 and 1). They just keep increasing the bandwidth each gen while keeping everything else the same. This way they can keep all the hardware backwards/forwards compatible.

The AM4 socket supports 24 lanes of PCIe; 4 of these lanes are reserved for the chipset (X470/B450/etc) and is what's used for all the I/O the chipsest handles (SATA,NIC,Extra PCIe lanes/etc). It's up to the board manufacturer how the other 20 lanes are used; generally they use 4 for an NVME connector and a pair of PCIex16 connectors that can do x16 or x8x8.

When an add-in-board is plugged into one of these PCIe sockets the CPU and AIB auto-negotiate the fastest PCIe link speed they can both handle. Generally they both support PCIe3 so that's what's used but if you put in an older PCIe2 only card then the link speed will auto-negotiate down to that level and everything will 'just work'.

It's no different with PCIe4; the CPUs will start supporting 4 as their highest link speed and will try to use that initially but auto-negotiate down to 3 if that's the fastest that the AIB supports.

Theoretically if the PCIe traces between an x16 slot and the CPU on a current AM4 board are overbuilt enough to handle the increased bandwidth that PCIe4 brings then that board would start supporting PCIe4 when you dropped in a new CPU and AIB that both supported it. Now there's tons of business/engineering reasons why this won't happen; but it's theoretically possible.

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I'm running FDS and the fire calculations end up very intense.

Protip: intense fire coming from your workstation is not part of the calculation!

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They won't need a new socket/pinout for PCIe 4 (or 5); the layout is exactly the same as 3 (and 2 and 1). They just keep increasing the bandwidth each gen while keeping everything else the same. This way they can keep all the hardware backwards/forwards compatible.

The AM4 socket supports 24 lanes of PCIe; 4 of these lanes are reserved for the chipset (X470/B450/etc) and is what's used for all the I/O the chipsest handles (SATA,NIC,Extra PCIe lanes/etc). It's up to the board manufacturer how the other 20 lanes are used; generally they use 4 for an NVME connector and a pair of PCIex16 connectors that can do x16 or x8x8.

When an add-in-board is plugged into one of these PCIe sockets the CPU and AIB auto-negotiate the fastest PCIe link speed they can both handle. Generally they both support PCIe3 so that's what's used but if you put in an older PCIe2 only card then the link speed will auto-negotiate down to that level and everything will 'just work'.

It's no different with PCIe4; the CPUs will start supporting 4 as their highest link speed and will try to use that initially but auto-negotiate down to 3 if that's the fastest that the AIB supports.

Theoretically if the PCIe traces between an x16 slot and the CPU on a current AM4 board are overbuilt enough to handle the increased bandwidth that PCIe4 brings then that board would start supporting PCIe4 when you dropped in a new CPU and AIB that both supported it. Now there's tons of business/engineering reasons why this won't happen; but it's theoretically possible.

All this to say it's theoretically possible? It ain't happening.

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Theoretically if the PCIe traces between an x16 slot and the CPU on a current AM4 board are overbuilt enough to handle the increased bandwidth that PCIe4 brings then that board would start supporting PCIe4 when you dropped in a new CPU and AIB that both supported it. Now there's tons of business/engineering reasons why this won't happen; but it's theoretically possible.

The difference between PCIe-3 and 4 is pretty substantial, going from 8Gbit/sec/pin to 16Gbit/sec/pin isn't trivial. A lot of really wonky poo poo starts to happen when your signaling frequency gets that high. The signal integrity might require additional ground pins connected directly to the cpu in order to get the lanes to work at the high speeds it needs. Or they might use repeaters or conditioners and eat the very tiny latency increase. No idea how the poor engineers are gonna make it work, just that it's probably not gonna be super duper fun to do it.

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Heres a partial answer to PCIe4 chat. First Rome specific board spotted in the wild.

AnandTech posted:

However, one of the new features of Rome is the use of PCIe 4.0. PCIe 4.0 has different standards for on-board signalling in order to get the required speed, so even though the processors are backwards compatible with PCIe 3.0, we expect new motherboards and new systems to be developed with PCIe 4.0 specifications in mind.
...
On this board, the PCIe slots are labelled in PCIe 3 and PCIe 4 modes Almost all of them say PCIe 4 compatible – this is just listing the peak support, the PCIe 4.0 slots also do PCIe 3.0 with Naples processors. It is worth nothing that the ones nearest the processor are the PCIe 4.0 slots, and the ones furthest away are the PCIe 3.0 slots. This might be down to trace length limits to ensure PCIe 4.0 speeds.

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I guess that means PCIe extenders are dead now.

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It might be an issue to use them at 4.0 speeds, but presumably they'll still work fine at 3.0 which will still be fast enough for many purposes for a long time.

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I guess that means PCIe extenders are dead now.

your video card is perfectly happy without pcie 4.0

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Jun 10, 2001

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Perhaps more budget oriented boards deliver 8x pci 4 lanes to graphics cards and 2x to NVME. This decreases pin counts from the CPU, and allows for more storage lanes. There's a million configurations one could imagine. I suspect aside from multi card compute, you won't need more than the bandwidth of 8x pcie4 or 16x pcie3 for years.

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